ST10F276E
Bootstrap loader
The values for operand0, operand1 and the signature should be such that the sequence
shown in the figure below is successfully executed.
MOV
ADD
Rx, CheckBlock1Addr; 00’0000h for standard reset
Rx, CheckBlock2Addr; 00’1FFCh for standard reset
CPLB
RLx
; 1s complement of the lower
; byte of the sum
CMP
Rx, CheckBlock3Addr; 00’1FFEh for standard reset
5.6.9
Alternate boot user software aspects
User defined alternate boot code must start at 09’0000h. A new SFR created on the
ST10F276E indicates that the device is running in Alternate Boot Mode: Bit 5 of EMUCON
(mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration.
All the other bits are ignored when checking the content of this register to read the value of
bit 5.
This bit is a read-only bit. It remains set until the next software or hardware reset.
5.6.10
EMUCON register
EMUCON (FE0Ah / 05h)
15 14 13 12
SFR
8
Reset value: - xxh:
11
10
9
7
6
5
ABM
R
4
3
2
1
0
-
-
-
Table 36. ABM bit description
Bit
Function
ABM Flag (or TMOD3)
0: Alternate Boot Mode is not selected by reset configuration on P0L[5..4]
ABM
1: Alternate Boot Mode is selected by reset configuration on P0L[5..4]: This bit is
set if P0L[5..4] = ‘01’ during hardware reset.
5.6.11
Internal decoding of test modes
The test mode decoding logic is located inside the ST10F276E Bus Controller.
The decoding is as follows:
●
●
●
Alternate Boot Mode decoding: (P0L.5 & P0L.4)
Standard Bootstrap decoding: (P0L.5 & P0L.4)
Normal operation: (P0L.5 & P0L.4)
The other configurations select ST internal test modes.
Doc ID 12303 Rev 3
69/235
STMICROELECTRONICS [ ST ]
