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ST10F276S-4T3 参数 Datasheet PDF下载

ST10F276S-4T3图片预览
型号: ST10F276S-4T3
PDF下载: 下载PDF文件 查看货源
内容描述: 16位MCU与MAC单元832 KB的闪存和68 KB的RAM [16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM]
分类和应用: 闪存
文件页数/大小: 235 页 / 2491 K
品牌: STMICROELECTRONICS [ ST ]
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Central processing unit (CPU)  
ST10F276E  
6
Central processing unit (CPU)  
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and  
dedicated SFRs. Additional hardware has been added for a separate multiply and divide  
unit, a bit-mask generator and a barrel shifter.  
Most of the ST10F276E’s instructions can be executed in one instruction cycle which  
requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are  
processed in one instruction cycle independent of the number of bits to be shifted.  
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x  
16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.  
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from  
2 cycles to 1 cycle.  
The CPU uses a bank of 16 word registers to run the current context. This bank of General  
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.  
A Context Pointer (CP) register determines the base address of the active register bank to  
be accessed by the CPU.  
The number of register banks is only restricted by the available Internal RAM space. For  
easy parameter passing, a register bank may overlap others.  
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system  
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack  
pointer (SP) register.  
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer  
value upon each stack access for the detection of a stack overflow or underflow.  
Figure 14. CPU Block Diagram (MAC Unit not included)  
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Doc ID 12303 Rev 3  
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