ST10F276E
Central processing unit (CPU)
6.1
Multiplier-accumulator unit (MAC)
The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to
improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle.
This new coprocessor (so-called MAC) contains a fast multiply-accumulate unit and a repeat
unit.
The coprocessor instructions extend the ST10 CPU instruction set with multiply, multiply-
accumulate, 32-bit signed arithmetic operations.
Figure 15. MAC unit architecture
Operand 1
Operand 2
16
16
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
16 x 16
signed/unsigned
Multiplier
QX0 IDX Offset Register
QX1 IDX Offset Register
Concatenation
32
32
Mux
Sign Extend
Scaler
MRW
0h
08000h
0h
40
40
40 40
Mux
40
Mux
Repeat Unit
MCW
Interrupt
Controller
40
A
40
B
ST10 CPU
40-bit Signed Arithmetic Unit
MSW
40
Flags MAE
MAH
MAL
Control Unit
40
8-bit Left/Right
Shifter
Doc ID 12303 Rev 3
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STMICROELECTRONICS [ ST ]
