ST10F276E
Electrical characteristics
Figure 68. SSC master timing
T
T
T
ꢈꢉꢁ
ꢈꢉꢉ
ꢈꢉꢀ
ꢍꢀꢏ
ꢍꢁꢏ
3#,+
T
T
ꢈꢉꢈ
ꢈꢉꢇ
T
ꢈꢉꢃ
T
T
T
ꢈꢉꢃ
ꢈꢉꢃ
ꢈꢉꢄ
-432
-234
ꢀST OUT BIT
ꢁND OUT BIT
,AST OUT BIT
T
T
T
T
ꢈꢉꢆ
ꢈꢉꢊ
ꢈꢉꢆ
ꢈꢉꢊ
ꢁND IN BIT
ꢀST IN BIT
,AST IN BIT
'!0'2)ꢉꢉꢀꢇꢃ
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
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