Electrical characteristics
ST10F276E
23.8.21 External bus arbitration
V
DD = 5V 10%, VSS = 0V, T = -40 to +125°C, C = 50pF
A
L
Table 107. External bus arbitration
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU Clock
1/2 TCL = 1 to 64 MHz
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
HOLD input setup time
to CLKOUT
t
t
t
61 SR
62 CC
63 CC
18.5
-
-
18.5
-
CLKOUT to HLDA high
or BREQ low delay
12.5
12.5
CLKOUT to HLDA low
or BREQ high delay
-
ns
t
t
t
t
64 CC CSx release 1
20
15
20
15
20
15
20
15
65 CC CSx drive
- 4
-
- 4
-
66 CC Other signals release 1
67 CC Other signals drive
- 4
- 4
Figure 66. External bus arbitration (releasing the bus)
#,+/54
T
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T
ꢄꢈ
ꢀꢏ
T
T
ꢄꢁ
"2%1
ꢁꢏ
ꢈꢏ
ꢄꢇ
#3X
ꢍ0ꢄꢌXꢏ
T
ꢄꢄ
ꢀꢏ
/THERS
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1. The ST10F276E will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
.
64
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
