ST10F276E
Electrical characteristics
Figure 69. SSC slave timing
T
T
T
ꢈꢀꢁ
ꢈꢀꢉ
ꢈꢀꢀ
ꢍꢀꢏ
ꢍꢁꢏ
3#,+
Tꢈꢀꢇ
T
ꢈꢀꢈ
T
T
T
ꢈꢀꢃ
T
ꢈꢀꢃ
ꢈꢀꢄ
ꢈꢀꢃ
ꢀST OUT BIT
ꢁND OUT BIT
,AST OUT BIT
T
-234
-432
T
T
T
ꢈꢀꢊ
ꢈꢀꢆ
ꢈꢀꢊ
ꢈꢀꢆ
ꢀST IN BIT
ꢁND IN BIT
,AST IN BIT
'!0'2)ꢉꢉꢀꢇꢄ
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
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