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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
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M25PE10, M25PE20  
Read Data Bytes (READ)  
next higher address after each Byte of data is shift-  
ed out. The whole memory can, therefore, be read  
with a single Read Data Bytes (READ) instruction.  
When the highest address is reached, the address  
counter rolls over to 000000h, allowing the read  
sequence to be continued indefinitely.  
The Read Data Bytes (READ) instruction is termi-  
nated by driving Chip Select (S) High. Chip Select  
(S) can be driven High at any time during data out-  
put. Any Read Data Bytes (READ) instruction,  
while an Erase, Program or Write cycle is in  
progress, is rejected without having any effects on  
the cycle that is in progress.  
The device is first selected by driving Chip Select  
(S) Low. The instruction code for the Read Data  
Bytes (READ) instruction is followed by a 3-Byte  
address (A23-A0), each bit being latched-in during  
the rising edge of Serial Clock (C). Then the mem-  
ory contents, at that address, is shifted out on Se-  
rial Data Output (Q), each bit being shifted out, at  
a maximum frequency f , during the falling edge of  
R
Serial Clock (C).  
The instruction sequence is shown in Figure 12.  
The first Byte addressed can be at any location.  
The address is automatically incremented to the  
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39  
C
Instruction  
24-Bit Address  
23 22 21  
MSB  
3
2
1
0
D
Q
Data Out 1  
Data Out 2  
High Impedance  
2
7
6
5
4
3
1
7
0
MSB  
AI03748D  
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.  
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