M24128, M24C64, M24C32
Figure 9.
Write cycle polling flowchart using ACK
Write cycle
in progress
Device operation
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
ReStart
Send address
and receive ACK
Stop
NO
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
4.10
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
w
) is
shown in
and
but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in
is:
–
–
–
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code
(the first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned
and the bus master goes back to Step 1. If the device has terminated the internal
Write cycle, it responds with an Ack, indicating that the device is ready to receive
the second part of the instruction (the first byte of this instruction having been sent
during Step 1).
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