Device operation
Figure 8.
WC
ACK
Byte Write
Start
Dev Select
R/W
ACK
M24128, M24C64, M24C32
Write mode sequences with WC = 0 (data write enabled)
ACK
Data in
ACK
Byte address
Byte address
WC
ACK
Page Write
Start
Dev Select
R/W
ACK
ACK
Data in 1
ACK
Data in 2
Byte address
Byte address
WC (cont'd)
ACK
Page Write
(cont'd)
Data in N
ACK
Stop
Stop
AI01106d
4.9
ECC (error correction code) and Write cycling
The M24128 and M24C64 in UFDFPN8 (MLP) 2 × 3 mm package offer an ECC (error
correction code) logic which compares each 4-byte word with its six associated EEPROM
ECC bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a
read operation, the ECC detects it and replaces it by the correct value. The read reliability is
therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of write cycles.
All M24C32, M24C64 and M24128 devices are qualified at 1 million (1 000 000) write
cycles; the M24128 and M24C64 in UFDFPN8 2 × 3 mm package are qualified (at 1 million
write cycles), using a cycling routine that writes to the device by multiples of 4-byte words.
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STMICROELECTRONICS [ STMICROELECTRONICS ]
