DC and AC parameters
Table 16.
Symbol
M24128, M24C64, M24C32
DC characteristics (V
CC
= 1.7 V to 5.5 V)
(1)
Parameter
Test condition
(in addition to those in
V
IN
= V
SS
or V
CC
device in Standby mode
V
OUT
= V
SS
or V
CC,
SDA in Hi-Z
V
CC
=1.7 V, f
c
= 400 kHz
During t
W
, 1.7 V < V
CC
< 2.5 V
V
IN
= V
SS
or V
CC
,
1.7 V < V
CC
< 2.5 V
–0.45
0.7V
CC
I
OL
= 0.7 mA, V
CC
= 1.7 V
Min.
Max.
Unit
I
LI
I
LO
I
CC
I
CC0
I
CC1
V
IL
V
IH
V
OL
Input leakage current
(SCL, SDA, E2, E1, E0)
Output leakage current
Supply current (Read)
Supply current (Write)
Standby supply current
Input low voltage (SDA,
SCL, WC)
Input high voltage (SDA,
SCL, WC)
Output low voltage
±2
±2
0.8
3
(2)
1
0.3 V
CC
V
CC
+0.6
0.2
µA
µA
mA
mA
µA
V
V
V
1. Preliminary data.
2. Characterized value, not tested in production.
Table 17.
AC characteristics (V
CC
= 2.5 V to 5.5 V or V
CC
= 1.8 V to 5.5 V)
Test conditions specified in
and
Symbol
f
C
t
CHCL
t
CLCH
t
DL1DL2(1)
t
DXCX
t
CLDX
t
CLQX
t
CLQV(2)
t
CHDX(3)
t
DLCL
t
CHDH
t
DHDL
t
W
Alt.
f
SCL
t
HIGH
t
LOW
t
F
Clock frequency
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
Clock pulse width high
Clock pulse width low
SDA fall time
600
1300
20
100
0
200
200
600
600
600
1300
5
(4)
900
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
t
SU:DAT
Data in setup time
t
HD:DAT
Data in hold time
t
DH
t
AA
Data out hold time
Clock low to next data valid (access time)
t
SU:STA
Start condition setup time
t
HD:STA
Start condition hold time
t
SU:STO
Stop condition setup time
t
BUF
t
WR
Time between Stop condition and next Start condition
Write time
1. Sampled only, not 100% tested.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3. For a reStart condition, or following a Write cycle.
4. For production lots assembled from 1
st
July 2007 (data code 727: week27, year 2007), the M24xxx-R
(1.8 V to 5.5 V range) memories are specified with t
W
= 5 ms (instead of 10ms).
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