ST24/25C02, ST24C02R, ST24/25W02
Table 7. AC Characteristics
(T
A
= 0 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
t
CH1CH2
t
CL1CL2
t
DH1DH2
t
DL1DL1
t
CHDX
(1)
Alt
t
R
t
F
t
R
t
F
t
SU:STA
t
HIGH
t
HD:STA
t
HD:DAT
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
AA
t
DH
f
SCL
t
WR
Clock Rise Time
Clock Fall Time
Input Rise Time
Input Fall Time
Parameter
Min
Max
1
300
1
300
Unit
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
µs
µs
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
Clock Frequency
Write Time
4.7
4
4
0
4.7
250
4.7
4.7
0.3
300
100
10
3.5
t
CHCL
t
DLCL
t
CLDX
t
CLCH
t
DXCX
t
CHDH
t
DHDL
t
CLQV (2)
t
CLQX
f
C
t
W (3)
µs
ns
kHz
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤
50ns
0.2V
CC
to 0.8V
CC
DEVICE OPERATION
(cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I
2
C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
Input and Output Timing Ref. Voltages 0.3V
CC
to 0.7V
CC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.3VCC
AI00825
0.2VCC
6/16
STMICROELECTRONICS [ STMICROELECTRONICS ]
