ST24/25C02, ST24C02R, ST24/25W02
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x02
ST25x02
ST24C02R
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI00789D
ST24x02
ST25x02
ST24C02R
VCC
MODE/WC
SCL
SDA
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI00790E
VCC
MODE/WC
SCL
SDA
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Input or Output Voltages
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Electrostatic Discharge Voltage (Machine model)
(3)
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.6 to 6.5
–0.3 to 6.5
4000
500
Unit
°C
°C
°C
V
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0
Ω).
DESCRIPTION
(cont’d)
The ST24/25x02 are 2K bit electrically erasable
programmable memories (EEPROM), organized
as 256 x 8 bits. They are manufactured in SGS-
THOMSON’s Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C02R only.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I
2
C stand-
ard, two wire serial interface which uses a bi-direc-
2/16
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I
2
C bus defini-
tion. This is used together with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 2K devices may be
attached to the I
2
C bus and selected individually.
The memories behave as a slave device in the I
2
C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
STMICROELECTRONICS [ STMICROELECTRONICS ]
