8 Mbit Firmware Hub
SST49LF008A
Data Sheet
TABLE 11: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
µs
1
TPU-WRITE
100
µs
T11.2 1161
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 12: Pin Impedance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
Pin Inductance
1
CIN
VIN = 0V
12 pF
2
LPIN
20 nH
T12.4 1161
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. Refer to PCI spec.
TABLE 13: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T13.3 1161
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: Clock Timing Parameters
Symbol
TCYC
THIGH
TLOW
-
Parameter
Min
30
11
11
1
Max
Units
CLK Cycle Time
ns
ns
CLK High Time
CLK Low Time
ns
CLK Slew Rate (peak-to-peak)
RST# or INIT# Slew Rate
4
V/ns
mV/ns
-
50
T14.1 1161
T
cyc
T
high
0.6 V
DD
T
low
0.5 V
DD
0.4 V
(minimum)
p-to-p
DD
0.4 V
DD
0.3 V
DD
0.2 V
DD
1161 F11.0
FIGURE 8: CLK Waveform
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
23
SST [ SILICON STORAGE TECHNOLOGY, INC ]
