8 Mbit Firmware Hub
SST49LF008A
Data Sheet
AC Characteristics (PP Mode)
TABLE 19: Read Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TRC
Parameter
Min
270
1
Max
Units
ns
Read Cycle Time
TRST
TAS
RST# High to Row Address Setup
R/C# Address Set-up Time
R/C# Address Hold Time
Address Access Time
µs
45
ns
TAH
45
ns
TAA
120
60
ns
TOE
Output Enable Access Time
OE# Low to Active Output
OE# High to High-Z Output
Output Hold from Address Change
ns
TOLZ
TOHZ
TOH
0
0
ns
35
ns
ns
T19.2 1161
TABLE 20: Program/Erase Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TRST
TAS
Parameter
Min
1
Max
Units
µs
RST# High to Row Address Setup
R/C# Address Setup Time
R/C# Address Hold Time
R/C# to Write Enable High Time
OE# High Setup Time
OE# High Hold Time
OE# to Data# Polling Delay
OE# to Toggle Bit Delay
WE# Pulse Width
50
50
50
20
20
ns
TAH
ns
TCWH
TOES
TOEH
TOEP
TOET
TWP
ns
ns
ns
40
40
ns
ns
100
100
50
ns
TWPH
TDS
WE# Pulse Width High
Data Setup Time
ns
ns
TDH
Data Hold Time
5
ns
TIDA
TBP
Software ID Access and Exit Time
Byte Programming Time
Sector-Erase Time
150
20
ns
µs
TSE
25
ms
ms
TBE
Block-Erase Time
25
TSCE
Chip-Erase Time
100
ms
T20.2 1161
TABLE 21: Reset Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TPRST
TRSTP
TRSTF
Parameter
Min
1
Max
Units
ms
ns
VDD stable to Reset Low
RST# Pulse Width
100
RST# Low to Output Float
48
ns
1
TRST
RST# High to Row Address Setup
RST# Low to reset during Sector-/Block-Erase or Program
RST# Low to reset during Chip-Erase
1
µs
TRSTE
TRSTC
10
50
µs
µs
T21.1 1161
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
27
SST [ SILICON STORAGE TECHNOLOGY, INC ]
