8 Mbit Firmware Hub
SST49LF008A
Data Sheet
TABLE 8: Operation Modes Selection (PP Mode)
Mode
Read
RST#
VIH
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIH
VIH
VIH
AIN
VIH
VIL
Sector or Block address,
XXH for Chip-Erase
Reset
VIL
VIH
X
X
VIL
X
X
High Z
X
X
X
Write Inhibit
X
High Z/DOUT
High Z/DOUT
VIH
VIH
Product Identification
VIH
VIL
Manufacturer’s ID (BFH) A18-A1=VIL, A0=VIL
Device ID2
A18-A1=VIL, A0=VIH
T8.6 1161
1. X can be VIL or VIH, but no other value.
2. Device ID = 5AH for SST49LF008A
Software Data Protection (SDP)
Data Protection
SST49LF008A provides the JEDEC approved Software
Data Protection scheme for all data alteration operation,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three-byte sequences. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
a six-byte load sequence. The SST49LF008A device is
shipped with the Software Data Protection permanently
enabled. See Table 9 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode, within TRC.
The SST49LF008A device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
19
SST [ SILICON STORAGE TECHNOLOGY, INC ]
