8 Mbit Firmware Hub
SST49LF008A
Data Sheet
AC Characteristics (FWH Mode)
TABLE 15: Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol
TCYC
TSU
Parameter
Min
30
7
Max
Units
ns
Clock Cycle Time
Data Set Up Time to Clock Rising
Clock Rising to Data Hold Time
Clock Rising to Data Valid
Byte Programming Time
Sector-Erase Time
ns
TDH
0
ns
1
TVAL
2
11
20
ns
TBP
µs
TSE
25
ms
ms
ms
ns
TBE
Block-Erase Time
25
TSCE
TON
TOFF
Chip-Erase Time
100
Clock Rising to Active (Float to Active Delay)
Clock Rising to Inactive (Active to Float Delay)
2
28
ns
T15.3 1161
1. Minimum and maximum times have different loads. See PCI spec.
TABLE 16: AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode)
Limits
Symbol
OH(AC)
Parameter
Min
Max
Units Test Conditions
I
Switching Current High
-12 VDD
mA 0 < VOUT ≤ 0.3VDD
-17.1(VDD-VOUT
)
mA 0.3VDD < VOUT < 0.9VDD
0.7VDD < VOUT <VDD
Equation C1
-32 VDD
(Test Point)
mA VOUT=0.7VDD
IOL(AC)
Switching Current Low
16 VDD
26.7 VOUT
Equation D1 mA VDD >VOUT ≥0.6VDD
mA 0.6VDD > VOUT > 0.1VDD
0.18VDD > VOUT > 0
(Test Point)
38 VDD
mA VOUT=0.18VDD
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-25+(VIN+1)/0.015
mA -3 < VIN ≤ -1
ICH
25+(VIN-VDD-1)/0.015
mA VDD+4 > VIN ≤ VDD+1
V/ns 0.2VDD-0.6VDD load
V/ns 0.6VDD-0.2VDD load
slewr2
slewf2
1
1
4
4
T16.3 1161
1. See PCI spec.
2. PCI specification output load is used.
TABLE 17: Reset Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol
TPRST
TKRST
TRSTP
TRSTF
Parameter
Min
1
Max
Units
ms
µs
VDD stable to Reset Low
Clock Stable to Reset Low
RST# Pulse Width
100
100
ns
RST# Low to Output Float
RST# High to FWH4 Low
RST# Low to reset during Sector-/Block-Erase or Program
48
10
ns
1
TRST
1
µs
TRSTE
µs
T17.5 1161
1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
24
SST [ SILICON STORAGE TECHNOLOGY, INC ]
