16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Address Dummy
Data
Maximum
Instruction
Description
Op Code Cycle1
0000 0011b (03H)
0000 1011b (0BH)
Cycle(s)2 Cycle(s) Cycle(s) Frequency
Read
Read Memory at 25 MHz
Read Memory at 80 MHz
3
3
0
1
1 to ∞
1 to ∞
25 MHz
80 MHz
High-Speed
Read
4 KByte Sec-
tor-Erase3
Erase 4 KByte of
memory array
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
3
3
3
0
0
0
0
0
0
0
0
0
80 MHz
80 MHz
80 MHz
80 MHz
32 KByte
Erase 32 KByte block
of memory array
Block-Erase4
64 KByte
Erase 64 KByte block
of memory array
Block-Erase5
Chip-Erase
Erase Full Memory Array
0110 0000b (60H)
or
1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H)
3
3
0
0
1
80 MHz
80 MHz
AAI-Word-Pro- Auto Address Increment
1010 1101b (ADH)
2 to ∞
gram6
Programming
RDSR7
Read-Status-Register
0000 0101b (05H)
0
0
0
0
1 to ∞
0
80 MHz
80 MHz
EWSR
Enable-Write-Status-Reg- 0101b 0000b
ister
(50H)
WRSR
WREN
WRDI
RDID8
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
0
0
0
3
0
0
0
0
1
0
80 MHz
80 MHz
80 MHz
80 MHz
0
1001 0000b (90H)
or
1 to ∞
1010 1011b (ABH)
JEDEC-ID
EBSY
JEDEC ID read
1001 1111b (9FH)
0
0
0
0
3 to ∞
0
80 MHz
80 MHz
Enable SO to output RY/BY# 0111 0000b (70H)
status during AAI program-
ming
DBSY
Disable SO as RY/BY#
status during AAI program-
ming
1000 0000b (80H)
0
0
0
80 MHz
T5.0 1271
1. One bus cycle is eight clock periods.
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
9
SST [ SILICON STORAGE TECHNOLOGY, INC ]
