16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
Memory Organization
The SST25VF016B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with
32 KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF016B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF016B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 0
MODE 3
MODE 0
SCK
SI
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CARE
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
SO
1271 SPIprot.0
Figure 3: SPI Protocol
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
5
SST [ SILICON STORAGE TECHNOLOGY, INC ]
