16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
2. Address bits above the most significant bit of each density can be VIL or VIH
.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be
programmed into the
initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufac-
turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read. The device outputs the data starting from the
specified address location. The data output stream is continuous through all addresses until termi-
nated by a low to high transition on CE#. The internal address pointer will automatically increment until
the highest memory address is reached. Once the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-around) of the address space. Once the
data from address location 1FFFFFH has been read, the next output will be from address location
000000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-
A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read
sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63 64
70
24
32
MODE 0
SCK
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
OUT
N+1
N+2
N+3
N+4
D
OUT
D
D
D
D
OUT
OUT
OUT
SO
MSB
1271 ReadSeq.0
Figure 5: Read Sequence
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
10
SST [ SILICON STORAGE TECHNOLOGY, INC ]
