欢迎访问ic37.com |
会员登录 免费注册
发布采购

SST25VF016B_11 参数 Datasheet PDF下载

SST25VF016B_11图片预览
型号: SST25VF016B_11
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位的SPI串行闪存 [16 Mbit SPI Serial Flash]
分类和应用: 闪存
文件页数/大小: 31 页 / 3300 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
 浏览型号SST25VF016B_11的Datasheet PDF文件第2页浏览型号SST25VF016B_11的Datasheet PDF文件第3页浏览型号SST25VF016B_11的Datasheet PDF文件第4页浏览型号SST25VF016B_11的Datasheet PDF文件第5页浏览型号SST25VF016B_11的Datasheet PDF文件第7页浏览型号SST25VF016B_11的Datasheet PDF文件第8页浏览型号SST25VF016B_11的Datasheet PDF文件第9页浏览型号SST25VF016B_11的Datasheet PDF文件第10页  
16 Mbit SPI Serial Flash  
SST25VF016B  
A Microchip Technology Company  
Data Sheet  
Hold Operation  
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-  
ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#  
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The  
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.  
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device  
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the  
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode  
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.  
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.  
If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as  
HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the  
device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 24 for Hold  
timing.  
SCK  
HOLD#  
Active  
Hold  
Active  
Hold  
Active  
1271 HoldCond.0  
Figure 4: Hold Condition Waveform  
Write Protection  
SST25VF016B provides software Write protection. The Write Protect pin (WP#) enables or disables  
the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL)  
in the status register provide Write protection to the memory array and the status register. See Table 4  
for the Block-Protection description.  
Write Protect Pin (WP#)  
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.  
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by  
the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.  
Table 2: Conditions to Execute Write-Status-Register (WRSR) Instruction  
WP#  
BPL  
1
Execute WRSR Instruction  
Not Allowed  
L
L
0
Allowed  
H
X
Allowed  
T2.0 1271  
©2011 Silicon Storage Technology, Inc.  
S71271-04-000  
01/11  
6