16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
High-Speed-Read (80 MHz)
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location 1FFFFFH has been read, the next output will be from address location 000000H.
CE#
MODE 3
MODE 0
0
1
2
3
4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
0B
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
X
SI
MSB
N
N+1
N+2
N+3
N+4
D
D
D
D
D
SO
OUT
OUT
OUT
OUT
OUT
MSB
1271 HSRdSeq.0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V or V
)
IH
IL
Figure 6: High-Speed-Read Sequence
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
24
32
MODE 0
SCK
02
ADD.
MSB
ADD.
ADD.
D
IN
MSB LSB
SI
MSB
HIGH IMPEDANCE
SO
1271 ByteProg.0
Figure 7: Byte-Program Sequence
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
