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CYW305OXCT 参数 Datasheet PDF下载

CYW305OXCT图片预览
型号: CYW305OXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 变频控制器系统恢复英特尔集成众核逻辑 [Frequency Controller with System Recovery for Intel Integrated Core Logic]
分类和应用: 晶体外围集成电路光电二极管控制器时钟
文件页数/大小: 20 页 / 183 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W305B  
Byte 6: Vendor ID & Revision ID Register (Read Only)  
Bit  
Name  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Revision_ID3  
Revision_ID2  
Revision_ID1  
Revision_ID0  
Vendor_ID3  
Vendor_ID2  
Vendor _ID1  
Vendor _ID0  
0
0
0
0
1
0
0
0
Revision ID bit[3]  
Revision ID bit[2]  
Revision ID bit[1]  
Revision ID bit[0]  
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.  
Byte 7: Control Register 7  
Bit  
Bit 7  
Pin#  
-
Name  
Reserved  
Default  
Pin Description  
0
1
1
1
1
1
1
0
Reserved  
Bit 6  
24  
23  
22  
24  
23  
22  
--  
24_48MHz_DRV  
48MHz_DRV  
48MHz_DRV  
24_48MHz  
48 MHz  
0 = Norm, 1 = High Drive  
0 = Norm, 1 = High Drive  
0 = Norm, 1 = High Drive  
(Active/Inactive)  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
(Active/Inactive)  
Bit 1  
48 MHz  
(Active/Inactive)  
Bit 0  
Reserved  
Reserved  
Byte 8: Watchdog Timer Register  
Bit  
Name  
PCI_Skew1  
PCI_Skew0  
Default  
Pin Description  
Bit 7  
Bit 6  
0
0
PCI skew control  
00 = Normal  
01 = –500ps  
10 = Reserved  
11 = +500ps  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
WD_TIMER4  
WD_TIMER3  
WD_TIMER2  
WD_TIMER1  
WD_TIMER0  
WD_PRE_SCALER  
1
1
1
1
1
0
These bits store the time-out value of the Watchdog timer. The scale of the  
timer is determine by the pre-scaler.  
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set  
to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5  
sec. to 80 sec.  
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.  
0 = 150 ms  
1 = 2.5 sec  
Byte 9: System RESET and Watchdog Timer Register  
Bit  
Name  
Default  
Pin Description  
SDRAM clock output drive strength  
0 = Normal  
Bit 7  
Bit 6  
Bit 5  
SDRAM_DRV  
0
1 = High Drive  
PCI_DRV  
0
0
PCI clock output drive strength  
0 = Normal  
1 = High Drive  
FS_Override  
0 = Select operating frequency by FS[4:0] input pins  
1 = Select operating frequency by SEL[4:0] settings  
Rev 1.0,November 20, 2006  
Page 9 of 20  
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