W305B
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Bit
Description
Bit
29
Acknowledge from slave
30:37
38
Data byte from slave – 8 bits
Not Acknowledge
Stop
39
W305B Serial Configuration Map
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
The serial bits will be read by the clock driver in the following
order:
All unused register bits (reserved and N/A) should be written
to a “0” level.
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SEL4
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
0
0
0
See Table 5
See Table 5
See Table 5
See Table 5
See Table 5
Spread Select2
Spread Select1
Spread Select0
‘000’ = Normal (spread off)
‘001’ = Test Mode
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = 0.5%
‘110’ = 0.25%
‘111’ = 0.38%
Byte 1: Control Register 1
Bit
Bit 7
Pin#
23
3
Name
Default
Description
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
X
X
X
X
X
0
Latched FS[4:0] inputs. These bits are read only.
Bit 6
Bit 5
13
12
11
-
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
3
REF2X
1
(Active/Inactive)
Reserved
Bit 0
-
Reserved
0
Byte 2: Control Register 2
Bit
Bit 7
Pin#
20
Name
PCI7
Default
Description
(Active/Inactive)
1
1
1
1
Bit 6
19
PCI6
(Active/Inactive)
Bit 5
18
PCI5
(Active/Inactive)
Bit 4
16
PCI4
(Active/Inactive)
Rev 1.0,November 20, 2006
Page 7 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
