W305B
Byte 2: Control Register 2 (continued)
Bit
Pin#
15
Name
Default
Description
Bit 3
Bit 2
Bit 1
Bit 0
PCI3
PCI2
PCI1
PCI0
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
13
12
11
Byte 3: Control Register 3
Bit
Bit 7
Pin#
Name
3V66_2
Default
Description
9
8
1
1
1
1
0
0
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved
Bit 6
3V66_1
3V66_0
APIC
Bit 5
7
Bit 4
55
-
Bit 3
Reserved
Reserved
CPU1
Bit 2
-
Reserved
Bit 1
51
52
(Active/Inactive)
(Active/Inactive)
Bit 0
CPU0
Byte 4: Control Register 4
Bit
Bit 7
Pin#
38
41
42
43
44
47
48
49
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Default
Description
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: Control Register 5
Bit
Bit 7
Pin#
-
Name
Reserved
Reserved
Reserved
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Default
Description
0
0
0
1
1
1
1
1
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
31
32
35
36
37
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 3
Bit 2
Bit 1
Bit 0
Rev 1.0,November 20, 2006
Page 8 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
