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CY28443ZXC-3 参数 Datasheet PDF下载

CY28443ZXC-3图片预览
型号: CY28443ZXC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢ Calistoga的芯片组 [Clock Generator for Intel㈢ Calistoga Chipset]
分类和应用: 时钟发生器
文件页数/大小: 23 页 / 242 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28443-3  
Byte 5: Control Register 5 (continued)  
Bit  
@Pup  
Name  
Description  
CPU[T/C]1 PWRDWN Drive Mode  
0 = Driven when PD asserted, 1 = Tri-state when PD asserted  
1
0
CPU[T/C]1  
0
0
CPU[T/C]0  
CPU[T/C]0 PWRDWN Drive Mode  
0 = Driven when PD asserted, 1 = Tri-state when PD asserted  
Byte 6: Control Register 6  
Bit  
@Pup  
Name  
Description  
7
0
TEST_SEL  
REF/N or Tri-state Select  
0 = Tri-state, 1 = REF/N Clock  
6
5
4
3
0
1
1
1
TEST_MODE  
REF1  
Test Clock Mode Entry Control  
0 = Normal operation, 1 = REF/N or Tri-state mode,  
REF0 Output Drive Strength  
0 = Low, 1 = High  
REF0  
REF0 Output Drive Strength  
0 = Low, 1 = High  
PCI, PCIF and SRC clock SW PCI_STP Function  
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert  
to free running  
When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will  
be stopped in a synchronous manner with no short pulses.  
When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will  
resume in a synchronous manner with no short pulses.  
2
1
0
HW  
HW  
HW  
FSC  
FSB  
FSA  
FSC Reflects the value of the FSC pin sampled on power-up  
0 = FSC was low during VTT_PWRGD# assertion  
FSB Reflects the value of the FSB pin sampled on power-up  
0 = FSB was low during VTT_PWRGD# assertion  
FSA Reflects the value of the FSA pin sampled on power-up  
0 = FSA was low during VTT_PWRGD# assertion  
Byte 7: Vendor ID  
Bit @Pup  
Name  
Revision Code Bit 3  
Revision Code Bit 2  
Revision Code Bit 1  
Revision Code Bit 0  
Vendor ID Bit 3  
Description  
Revision Code Bit 3  
Revision Code Bit 2  
Revision Code Bit 1  
Revision Code Bit 0  
Vendor ID Bit 3  
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
Vendor ID Bit 2  
Vendor ID Bit 2  
Vendor ID Bit 1  
Vendor ID Bit 1  
Vendor ID Bit 0  
Vendor ID Bit 0  
Byte 8: Control Register 8  
Bit  
@Pup  
Name  
Description  
7
6
0
CPU_SS  
0:–0.5% (Peak to peak)  
1: –1.0% (Peak to peak)  
0
CPU-DWN_SS  
0: Down Spread  
1: Center Spread  
5
4
3
2
0
0
0
1
RESERVED  
RESERVED  
RESERVED  
48M  
RESERVED, Set = 0  
RESERVED, Set = 0  
RESERVED, Set = 0  
48-MHz Output Drive Strength  
0 = Low, 1 = High  
Rev 1.0,November 20, 2006  
Page 7 of 23  
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