CY28443-3
Pin Descriptions (continued)
Pin No.
Name
Type
Description
52
REF1/FCTSEL0
I/O, SE Fixed 14.318-MHz Clock Output/3.3 LVTTL input for selecting for pin 14, 15
PD (DOT96[T/C], 27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or
100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 14
PIN 15
PIN 17
PIN 18
0
0
1
1
0
1
0
1
DOT96T
DOT96T
DOT96C
DOT96C
100MT_SST 100MC_SST
SRCT0
SRCC0
SRCC0
SRCC0
27M_non spread 27M_Spread SRCT0
OFF Low TBD SRCT0
53
FSC
I/O
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
54
55
56
CPU_STP#
PCI_STP#
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
I, PU 3.3V LVTTL input for PCI_STP# active LOW.
PCI2/SEL_CLKREQ# I/O, PD Fixed 33-MHz clock output/3.3V-tolerant input for CLKREQ# pins 32 and 33
selection
SE
(sampled on the VTT_PWRGD# assertion).
0 = CLKREQ#[A:B] functionality
1 = SRC[T/C]9 functionality
Table 1. Frequency Select Table FSA, FSB and FSC
FSC FSB FSA
CPU
SRC
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF0
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
1
0
0
0
0
0
1
1
1
1
1
0
100 MHz
133 MHz
166 MHz
200 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
48 MHz
48 MHz
48 MHz
48 MHz
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
one-shot functionality in that once
a
valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Rev 1.0,November 20, 2006
Page 3 of 23
SPECTRALINEAR [ SPECTRALINEAR INC ]
