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CY28443ZXC-3 参数 Datasheet PDF下载

CY28443ZXC-3图片预览
型号: CY28443ZXC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢ Calistoga的芯片组 [Clock Generator for Intel㈢ Calistoga Chipset]
分类和应用: 时钟发生器
文件页数/大小: 23 页 / 242 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28443-3  
Table 5. Crystal Recommendations  
Frequency  
Drive  
(max.)  
Shunt Cap Motional  
(max.)  
Tolerance  
(max.)  
Stability  
(max.)  
Aging  
(max.)  
(Fund)  
Cut  
Loading Load Cap  
(max.)  
14.31818 MHz  
AT  
Parallel 20 pF  
0.1 mW  
5 pF  
0.016 pF  
35 ppm  
30 ppm  
5 ppm  
The CY28443-3 requires a Parallel Resonance Crystal.  
Substituting a series resonance crystal will cause the  
CY28443-3 to operate at the wrong frequency and violate the  
ppm specification. For most applications there is a 300-ppm  
frequency shift between series and parallel crystals due to  
incorrect loading.  
Clock Chip  
Ci2  
Ci1  
Pin  
3 to 6p  
Crystal Loading  
Crystal loading plays a critical role in achieving low ppm perfor-  
mance. To realize low ppm performance, the total capacitance  
the crystal will see must be considered to calculate the appro-  
priate capacitive loading (CL).  
X2  
X1  
Cs2  
Cs1  
Trace  
2.8pF  
The following diagram shows a typical crystal configuration  
using the two trim capacitors. An important clarification for the  
following discussion is that the trim capacitors are in series  
with the crystal not parallel. It’s a common misconception that  
load capacitors are in parallel with the crystal and should be  
approximately equal to the load capacitance of the crystal.  
This is not true.  
XTAL  
Ce1  
Ce2  
Trim  
33pF  
Figure 2. Crystal Loading Example  
Use the following formulas to calculate the trim capacitor  
values for Ce1 and Ce2.  
Load Capacitance (each side)  
Ce = 2 * CL – (Cs + Ci)  
Total Capacitance (as seen by the crystal)  
1
CLe  
=
1
Ce2 + Cs2 + Ci2  
1
Ce1 + Cs1 + Ci1  
(
)
+
Figure 1. Crystal Capacitive Clarification  
Calculating Load Capacitors  
CL....................................................Crystal load capacitance  
CLe......................................... Actual loading seen by crystal  
using standard value trim capacitors  
In addition to the standard external trim capacitors, trace  
capacitance and pin capacitance must also be considered to  
correctly calculate crystal loading. As mentioned previously,  
the capacitance on each side of the crystal is in series with the  
crystal. This means the total capacitance on each side of the  
crystal must be twice the specified crystal load capacitance  
(CL). While the capacitance on each side of the crystal is in  
series with the crystal, trim capacitors (Ce1,Ce2) should be  
calculated to provide equal capacitive loading on both sides.  
Ce..................................................... External trim capacitors  
Cs..............................................Stray capacitance (terraced)  
Ci ...........................................................Internal capacitance  
(lead frame, bond wires etc.)  
CLK_REQ[0:1]# Description  
The CLKREQ#[A:B] signals are active LOW inputs used for  
clean enabling and disabling selected SRC outputs. The  
outputs controlled by CLKREQ#[A:B] are determined by the  
settings in register byte 8. The CLKREQ# signal is a  
de-bounced signal in that its state must remain unchanged  
during two consecutive rising edges of SRCC to be recognized  
as a valid assertion or deassertion. (The assertion and  
deassertion of this signal is absolutely asynchronous.)  
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)  
All differential outputs that were stopped are to resume normal  
operation in a glitch-free manner. The maximum latency from  
the assertion to active outputs is between 2–6 SRC clock  
periods (2 clocks are shown) with all SRC outputs resuming  
Rev 1.0,November 20, 2006  
Page 11 of 23  
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