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CY28443ZXC-3 参数 Datasheet PDF下载

CY28443ZXC-3图片预览
型号: CY28443ZXC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢ Calistoga的芯片组 [Clock Generator for Intel㈢ Calistoga Chipset]
分类和应用: 时钟发生器
文件页数/大小: 23 页 / 242 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28443-3  
simultaneously. All stopped SRC outputs must be driven HIGH  
within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater  
than 200 mV.  
drive mode bit) on the next diff clock# HIGH-to-LOW transition  
within 4 clock periods. When the SMBus PD drive mode bit  
corresponding to the differential (CPU, SRC, and DOT) clock  
output of interest is programmed to ‘0’, the clock outputs are  
held with the “Diff clock” pin driven HIGH at 2 x Iref, and “Diff  
clock#” tri-state. If the control register PD drive mode bit corre-  
sponding to the output of interest is programmed to “1”, then  
both the “Diff clock” and the “Diff clock#” are tri-state. Note the  
example in Figure 4 shows CPUT = 133 MHz and PD drive  
mode = ‘1’ for all differential outputs. This diagram and  
description is applicable to valid CPU frequencies 100, 133,  
166, and 200 MHz. In the event that PD mode is desired as  
the initial power-on state, PD must be asserted HIGH in less  
than 10 Ps after asserting Vtt_PwrGd#. It should be noted that  
96_100_SSC will follow the DOT waveform is selected for  
96 MHz and the SRC waveform when in 100-MHz mode.  
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)  
The impact of deasserting the CLKREQ#[A:B] pins is all SRC  
outputs that are set in the control registers to stoppable via  
deassertion of CLKREQ#[A:B] are to be stopped after their  
next transition. The final state of all stopped DIF signals is  
LOW, both SRCT clock and SRCC clock outputs will not be  
driven.  
PD (Power-down) Clarification  
The VTT_PWRGD# /PD pin is a dual-function pin. During  
initial power-up, the pin functions as VTT_PWRGD#. Once  
VTT_PWRGD# has been sampled LOW by the clock chip, the  
pin assumes PD functionality. The PD pin is an asynchronous  
active HIGH input used to shut off all clocks cleanly prior to  
shutting off power to the device. This signal is synchronized  
internal to the device prior to powering down the clock synthe-  
sizer. PD is also an asynchronous input for powering up the  
system. When PD is asserted HIGH, all clocks need to be  
driven to a low value and held prior to turning off the VCOs and  
the crystal oscillator.  
PD Deassertion  
The power-up latency is less than 1.8 ms. This is the time from  
the deassertion of the PD pin or the ramping of the power  
supply until the time that stable clocks are output from the  
clock chip. All differential outputs stopped in a three-state  
condition resulting from power down will be driven high in less  
than 300 Ps of PD deassertion to a voltage greater than  
200 mV. After the clock chip’s internal PLL is powered up and  
locked, all outputs will be enabled within a few clock cycles of  
each other. Figure 5 is an example showing the relationship of  
clocks coming up. It should be noted that 96_100_SSC will  
follow the DOT waveform is selected for 96 MHz and the SRC  
waveform when in 100-MHz mode.  
PD (Power-down) Assertion  
When PD is sampled HIGH by two consecutive rising edges  
of CPUC, all single-ended outputs will be held LOW on their  
next HIGH-to-LOW transition and differential clocks must held  
high or tri-stated (depending on the state of the control register  
CLKREQ#X  
SRCT(free running)  
SRCC(free running)  
SRCT(stoppable)  
SRCT(stoppable)  
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform  
Tstable  
<1.8 ms  
PD  
CPUT, 133MHz  
CPUC, 133MHz  
SRCT 100MHz  
SRCC 100MHz  
USB, 48MHz  
DOT96T  
DOT96C  
PCI, 33MHz  
REF  
Tdrive_PWRDN#  
<300 Ps, > 200 mV  
Figure 5. Power-down Deassertion Timing Waveform  
Rev 1.0,November 20, 2006  
Page 12 of 23  
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