CY28443-3
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3 ms
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 12. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay >0.25 ms
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8 ms
S0
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 13. Clock Generator Power-up/Run State Diagram
Rev 1.0,November 20, 2006
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