CY28346-2
AC Parameters (VDD = VDDA = 3.3V 5%) (continued)
66 MHz 100 MHz
133 MHz
200 MHz
Min. Max. Unit
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Notes
REF
Tdc
REF Duty Cycle
REF Period
45
69.84
1.0
55
71.0
4.0
45
69.84
1.0
55
71.0
4.0
45
69.84
1.0
55
71.0
4.0
45
69.84
1.0
55
71.0
4.0
%
ns
ns
8, 9
8, 9
Tperiod
Tr / Tf
REF Rise and Fall
Times
8, 21
Tccj
REF Cycle to Cycle
Jitter
1000
1000
1000
1000
ps
8, 9
Tpzl/Tpzh Output Enable
Delay (all outputs)
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
ns
ns
6
6
6
Tplz/Tpzh Output disable
delay (all outputs)
Tstable
All Clock Stabili-
zation from
Power-up
ms
Tss
Tsh
Tsu
Stopclock Set-up
Time
10.0
0
10.0
0
10.0
0
10.0
0
ns
ns
23
23
24
Stopclock Hold
Time
Oscillator Start-up
Time
1.2
1.2
1.2
1.2
ms
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
TPCB
ꢃꢃꢄꢀ:
Measurem ent Point
CPUT
2pF
ꢅꢆꢇ:
ꢃꢃꢄꢀ:
MULTSEL
TPCB
Measurem ent Point
CPUC
2pF
ꢂꢃꢄꢅ:
ꢂꢃꢄꢅ:
ꢀꢀꢁ:
Figure 15. 1.0V Test Load Termination
Notes:
23. CPU_STP# and PCI _STP# setup time with respect to any PCIF clock to guarantee that the effected clock will stop or start at the next PCIF clock’s rising edge.
24. When Crystal meets minimum 40-ohm device series resistance specification.
Rev 1.0,November 20, 2006
Page 17 of 19
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