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CY28346ZC-2 参数 Datasheet PDF下载

CY28346ZC-2图片预览
型号: CY28346ZC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器,差分CPU输出 [Clock Synthesizer with Differential CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 19 页 / 169 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28346ZC-2的Datasheet PDF文件第11页浏览型号CY28346ZC-2的Datasheet PDF文件第12页浏览型号CY28346ZC-2的Datasheet PDF文件第13页浏览型号CY28346ZC-2的Datasheet PDF文件第14页浏览型号CY28346ZC-2的Datasheet PDF文件第15页浏览型号CY28346ZC-2的Datasheet PDF文件第17页浏览型号CY28346ZC-2的Datasheet PDF文件第18页浏览型号CY28346ZC-2的Datasheet PDF文件第19页  
CY28346-2  
AC Parameters (VDD = VDDA = 3.3V 5%) (continued)  
66 MHz 100 MHz  
133 MHz  
200 MHz  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
Notes  
Tskew  
Unbuffered Skew  
3V66 to 3V66 Clock  
500  
250  
250  
500  
500  
250  
250  
500  
ps  
ps  
ps  
8, 9  
Tskew  
Buffered  
3V66 to 3V66 Clock  
Skew  
250  
250  
250  
250  
8, 9  
8, 9  
Tccj  
DRCG Cycle to  
Cycle Jitter  
66B  
Tdc  
66B(0:2) Duty Cycle  
45  
55  
45  
55  
45  
55  
45  
55  
%
8, 9  
Tr / Tf  
Tskew  
Tpd  
66B(0:2) Rise and  
Fall Times  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
ns  
8, 21  
Any 66B to Any 66B  
Skew  
175  
4.5  
175  
4.5  
175  
4.5  
175  
4.5  
ps  
ns  
ps  
8, 9  
8, 9  
66IN to 66B(0:2)  
Propagation Delay  
2.5  
2.5  
2.5  
2.5  
Tccj  
66B(0:2) Cycle to  
Cycle Jitter  
100  
100  
100  
100  
8, 9, 22  
PCI  
Tdc  
PCIF(0:2) PCI (0:6)  
Duty Cycle  
45  
55  
45  
55  
45  
55  
45  
30  
55  
%
8, 9  
5, 8, 9  
19  
Tperiod  
Thigh  
Tlow  
PCIF(0:2) PCI (0:6)  
period  
30.0  
12.0  
12.0  
0.5  
30.0  
12.0  
12.0  
0.5  
30.0  
12.0  
12.0  
0.5  
nS  
nS  
nS  
nS  
pS  
ps  
PCIF(0:2) PCI (0:6)  
high time  
12.0  
12.0  
0.5  
PCIF(0:2) PCI (0:6)  
low time  
20  
Tr/Tf  
PCIF(0:2) PCI (0:6)  
rise and fall times  
2.0  
500  
250  
2.0  
500  
250  
2.0  
500  
250  
2.0  
500  
250  
21  
Tskew  
Tccj  
Any PCI clock to  
Any PCI clock Skew  
8, 9  
8, 9  
PCIF(0:2) PCI (0:6)  
Cycle to Cycle Jitter  
48M_USB  
Tdc  
48M_USB Duty  
Cycle  
45  
55  
45  
55  
45  
55  
45  
55  
%
8, 9  
Tperiod  
Tr/Tf  
48M_USB Period  
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns  
8, 9  
48M_USB Rise and  
Fall Times  
1.0  
2.0  
1.0  
2.0  
1.0  
2.0  
1.0  
2.10  
ns  
8, 21  
Tccj  
48M_USB Cycle to  
Cycle Jitter  
350  
350  
350  
350  
ps  
5, 8, 9  
8, 9  
48M_DOT  
Tdc  
48M_DOT Duty  
Cycle  
45  
55  
45  
55  
45  
55  
45  
55  
%
Tperiod  
Tr/Tf  
48M_DOT Period  
20.837  
0.5  
20.837  
0.5  
20.837  
0.5  
20.837  
0.5  
ns  
ns  
8, 9  
8, 9  
48M_DOT Rise and  
Fall Times  
1.0  
1.0  
1.0  
1.0  
Tccj  
48M_DOT Cycle to  
Cycle Jitter  
350  
350  
350  
350  
ps  
8, 9  
Note:  
22. This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.  
Rev 1.0,November 20, 2006  
Page 16 of 19  
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