CY28341
AC Parameters (continued)
100 MHz
Min. Max.
133MHz
Min. Max
200 MHz
Min. Max
Parameter
Description
Unit
Notes[4]
Notes:
5. All outputs loaded as per maximum capacitive load table.
6. All outputs are not loaded.
7. This parameter is measured as an average over a 1-Ps duration, with a crystal center frequency of 14.31818 MHz.
8. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
9. When crystal meets minimum 40-ohm device series resistance specification.
10. Measured between 0.2V and 0.7V
.
DD
11. All outputs loaded as per loading specified in the Table 11.
DD
12. When X is driven from an external clock source (3.3V parameters apply).
IN
13. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
14. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
15. This measurement is applicable with Spread ON or spread OFF.
16. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals)
17. Probes are placed on the pins, and measurements are acquired at 0.4V.
18. The time specified is measured from when all VDD's reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the
specifications.
19. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
20. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
21. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts.
22. See Figure 10. for 0.7V loading specification.
23. Measured from Vol=0.175V to Voh=0.525V.
24. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
25. Measurement taken from differential waveform, from -0.35V to +0.35V.
26. Measured in absolute voltage, i.e. single-ended measurement.
27. Measured at VX between the rising edge and the following falling edge of the signal.
28. Measured at VX between the falling edge and the following rising edge of the signal.
29. This parameter is intended to be 0.45*Tperiod(min) for minimum spec. and 0.55*Tperiod(min) for maximum spec.
30. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode)
When PD# is sampled LOW by two consecutive rising edges
of CPU# clock then all clock outputs except CPU clocks must
be held LOW on their next HIGH to LOW transition. CPU
clocks must be held with the CPU clock pin driven HIGH with
a value of 2 x Iref, and CPU# undriven. Note that Figure 4
shows CPU = 133 MHz, this diagram and description is appli-
cable for all valid CPU frequencies 66, 100, 133, 200MHz.Due
to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
PW RDW N#
CPUT 133M Hz
CPUT# 133M Hz
PCI 33M Hz
AGP 66M Hz
USB 48M Hz
REF 14.318M Hz
DDRT 133M Hz
DDRC 133M Hz
SDRAM 133M Hz
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
Rev 1.0,November 20, 2006
Page 13 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
