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CY28341OCT 参数 Datasheet PDF下载

CY28341OCT图片预览
型号: CY28341OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 通用单芯片时钟解决方案VIA P4M266 / KM266 DDR系统 [Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341  
Power-down Deassertion (K7 Mode)  
When de-asserted PD# to HIGH level, all clocks are enabled  
and start running on the rising edge of the next full period in  
order to guarantee a glitch-free operation, no partial clock  
pulses.  
<1.5 msec  
PW RDW N#  
CPU 133MHz  
CPU# 133MHz  
PCI 33MHz  
AGP 66MHz  
USB 48MHz  
REF 14.318MHz  
DDRT 133MHz  
DDRC 133MHz  
SDRAM 133MHz  
Figure 5. Power-down Deassertion Timing Waveform (in K7 mode)  
VID (0:3),  
SEL (0,1)  
VTT_PWRGD#  
PWRGD  
0.2-0.3mS  
Delay  
Wait for  
VTT_GD#  
Sample Sels  
VDD Clock Gen  
Clock State  
State 0  
Off  
State 1  
State 2  
State 3  
(Note A)  
On  
Clock Outputs  
Clock VCO  
On  
Off  
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)[31]  
Note:  
31. This time diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power-up. After the first HIGH to LOW transition of VTT_PWRGD#, device  
is not affected, VTT_PWRGD# is ignored.  
Rev 1.0,November 20, 2006  
Page 15 of 19  
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