CY28341
AC Parameters (continued)
100 MHz
133MHz
200 MHz
Parameter
THIGH
TLOW
Description
Min.
Max.
Min.
Max
Min.
Max
Unit
ns
Notes[4]
11,16
PCI(_F,1:6) HIGH Time
12.0
12.0
0.5
12.0
12.0
0.5
12.0
12.0
0.5
PCI(_F,1:6) LOW Time
ns
11,17
Tr / Tf
PCI(_F,1:6) Rise and Fall Times
Any PCI to Any PCI Clock Skew
PCI(_F,1:6) Cycle to Cycle Jitter
2.5
500
500
2.5
500
500
2.5
500
500
ns
11,13
TSKEW
TCCJ
ps
11,15
ps
11,14,15
48MHz
TDC
48MHz Duty Cycle
45
55
45
55
45
55
%
7,11,14
7,11,14
11,13
TPeriod
Tr / Tf
TCCJ
48MHz Period
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns
48MHz Rise and Fall Times
48MHz Cycle to Cycle Jitter
1.0
4.0
1.0
4.0
1.0
4.0
ns
ps
500
500
500
11,14,15
24MHz
TDC
24MHz Duty Cycle
45
41.660
1.0
55
41.667
4.0
45
55
45
55
%
ns
ns
ps
7,11,14
7,11,14
11,13
TPeriod
Tr / Tf
TCCJ
24MHz Period
41.660 41.667 41.660 41.667
24MHz Rise and Fall Times
24MHz Cycle to Cycle Jitter
1.0
4.0
1.0
4.0
500
500
500
11,14,15
REF
TDC
REF Duty Cycle
45
69.8413
1.0
55
71.0
4.0
45
69.8413
1.0
55
71.0
4.0
45
69.8413
1.0
55
71.0
4.0
%
ns
ns
ps
7,11,14
7,11,14
11,13
TPeriod
Tr / Tf
TCCJ
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
1000
1000
1000
11,14,15
DDR
VX
Crossing Point Voltage of
DDRT/C
0.5*VDD 0.5*VDDD+ 0.5*VDD 0.5*VDD 0.5*VDD 0.5*VDD
D–0.2
V
V
19
20
– 0.2
0.2
D – 0.2 D+ 0.2
D+0.2
VD
Differential Voltage Swing
0.7
VDDD + 0.6
0.7
VDDD
0.6
+
0.7
VDDD
0.6
+
TDC
DDRT/C(0:5) Duty Cycle
DDRT/C(0:5) Period
45
9.85
1
55
10.2
3
45
14.85
1
55
15.3
3
45
9.85
1
55
10.2
3
%
ns
21
21
13
TPeriod
Tr / Tf
DDRT/C(0:5) Rise/Fall Slew
Rate
V/ns
TSKEW
TCCJ
DDRT/C to Any DDRT/C Clock
Skew
100
75
100
75
100
75
ps
ps
11,15,21
11,15,21
DDRT/C(0:5) Cycle to Cycle
Jitter
THPJ
DDRT/C(0:5) Half-period Jitter
BUF_IN to Any DDRT/C Delay
FBOUT to Any DDRT/CSkew
100
4
100
4
100
4
ps
ns
ps
11,15,21
11,14
11,14
18
TDelay
TSKEW
tstable
1
1
1
100
3
100
3
100
3
All Clock Stabilization from
Power-up
ms
Rev 1.0,November 20, 2006
Page 12 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
