CY28341
Power-down Deassertion (P4 Mode)
The power-up latency needs to be less than 3 mS.
< 1 .5 m se c
P W R D W N #
C P U 1 3 3 M H z
C P U # 1 3 3 M H z
P C I 3 3 M H z
A G P 6 6 M H z
U S B 4 8 M H z
R E F 1 4 .3 1 8 M H z
D D R T 1 3 3 M H z
D D R C 1 3 3 M H z
S D R A M 1 3 3 M H z
Figure 3. Power-down Deassertion Timing Waveform (in P4 Mode)
AMD K7 Processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
by two consecutive rising edges of CPU clock, then all affected
clocks are stopped in a LOW state as soon as possible. When
in power-down (and before power is removed), all outputs are
synchronously stopped in a LOW state (see figure3 below), all
PLL's are shut off, and the crystal oscillator is disabled. When
the device is shutdown, the I2C function is also disabled.
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) LOW, the device
transitions to a shutdown (power-down) mode and all power
supplies may then be removed. When PD# is sampled LOW
PW RDW N#
CPUOD_T 133M Hz
CPUCS_T 133M Hz
CPUOD_C 133M Hz
CPUCS_C 133M Hz
PCI 33M Hz
AGP 66M Hz
USB 48M Hz
REF 14.318M Hz
DDRT 133M Hz
DDRC 133M Hz
SDRAM 133M Hz
Figure 4. Power-down Assertion Timing Waveform (in K7 Mode)
Rev 1.0,November 20, 2006
Page 14 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
