CY28341
Maximum Ratings[3]
This device contains circuitry to protect inputs against damage
due to high-static voltages or electric field. However, precau-
tions should be take to avoid application of any voltage higher
than the maximum-rated voltages to this circuit. For proper
operation, VIN and VOUT should be constrained to the range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65qC to + 150qC
Operating Temperature:.................................... 0qC to +70qC
Maximum ESD.............................................................2000V
Maximum Power Supply:................................................5.5V
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V 5%, VDDI = VDD = 2.5V 5%, TA = 0°C to +70°C
Parameter
VIL1
VIH1
VIL2
VIH2
Vol
Description
Input Low Voltage
Conditions
Min.
Typ. Max.
Unit
Vdc
Vdc
Vdc
Vdc
V
Applicable to PD#, F S(0:4)
0.8
Input High Voltage
2.0
Input Low Voltage
Applicable to SDATA and SCLK
1.0
Input High Voltage
2.2
0.4
24
Output Low Voltage for SRESET#
Pull-down Current for SRESET#
Three-state Leakage Current
Dynamic Supply Current
Dynamic Supply Current
Power-down Supply Current
Internal Pull-up Device Current
Internal Pull-down Device Current
Input Pin Capacitance
IOL
Iol
VOL = 0.4V
35
mA
PA
mA
mA
PA
PA
PA
pF
Ioz
10
Idd3.3V
Idd2.5V
Ipd
CPU Frequency Set at 133.3 MHz[5]
CPU Frequency Set at 133.3 MHz[5]
PD# = 0
150
175
95
190
195
600
–25
10
5
Ipup
Input @ VSS
Ipdwn
Cin
Input @ VDD
Cout
Lpin
Output Pin Capacitance
Pin Inductance
6
pF
7
pF
Cxtal
Crystal Pin Capacitance
Measured from the XIN or XOUT to VSS 27
36
45
pF
AC Parameters
100 MHz
133MHz
200 MHz
Parameter
XTAL
Description
Min.
Max.
Min.
Max
Min.
Max
Unit
Notes[4]
TDC
X
IN Duty Cycle
45
69.841
0.7VDD
0
55
71.0
VDD
0.3VDD
10.0
500
45
69.84
0.7VDD
0
55
71.0
VDD
0.3VDD
10
45
69.84
0.7VDD
0
55
71.0
VDD
0.3VDD
10
%
ns
V
7,8
7,8
9
TPeriod
VHIGH
VLOW
Tr/Tf
XIN Period
X
IN High Voltage
IN Low Voltage
X
V
10
XIN Rise and Fall Times
IN Cycle to Cycle Jitter
Crystal Start-up Time
ns
ps
ms
10
TCCJ
Txs
X
500
500
11,12
12,9
30
30
30
P4 Mode CPU at 0.7V
TDC
CPUT/C Duty Cycle
45
55
45
55
45
55
%
7,11,14,21,
22
TPeriod
Tr/Tf
CPUT/C Period
9.85
175
10.2
7.35
175
7.65
4.85
175
5.1
ns 7,11,14,21,
22
CPUT/C Rise and Fall Times
Rise/Fall Matching
700
20%
125
700
20%
125
700
20%
125
ps
23,24
23,26,24
11,23,22
Delta Tr/Tf Rise/Fall Time Variation
ps
Notes:
3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All notes for this table may be found at the end of the table, on page 13.
Rev 1.0,November 20, 2006
Page 10 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
