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S71GL064A80BAI0F3 参数 Datasheet PDF下载

S71GL064A80BAI0F3图片预览
型号: S71GL064A80BAI0F3
PDF下载: 下载PDF文件 查看货源
内容描述: 堆叠式多芯片产品( MCP )闪存和RAM [Stacked Multi-Chip Product (MCP) Flash Memory and RAM]
分类和应用: 闪存
文件页数/大小: 102 页 / 1762 K
品牌: SPANSION [ SPANSION ]
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A d v a n c e I n f o r m a t i o n  
Data Retention Characteristics (4M Version G)  
Item  
Symbol  
VDR  
Test Condition  
VCC-0.2V (Note 1), VIN 0V. BYTE# = VSS or VCC 1.5  
VCC=1.5V, CS1# VCC-0.2V (Note 1), VIN  
Min  
Typ  
Max Unit  
VCC for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
CS1#  
-
-
-
-
3.3  
3
V
IDR  
0V  
-
0
µA  
tSDR  
tRDR  
-
See data retention waveform  
ns  
tRC  
-
Notes:  
1. CS1 controlled:CS1#V -0.2V. CS2 controlled: CS2 0.2V.  
CC  
Data Retention Characteristics (8M Version C)  
Item  
Symbol  
VDR  
Test Condition  
VCC-0.2V (Note 1). BYTE# = VSS or VCC  
VCC=3.0V, CS1# VCC-0.2V (Note 1)  
Min  
1.5  
-
Typ  
Max Unit  
VCC for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
CS1#  
-
-
-
-
3.3  
15  
-
V
IDR  
µA  
tSDR  
tRDR  
0
See data retention waveform  
ns  
tRC  
-
Notes:  
1. CS1 controlled:CS1#VCC-0.2V. CS2 controlled: CS2 0.2V.  
Data Retention Characteristics (8M Version D)  
Item  
Symbol  
VDR  
Test Condition  
Min  
1.5  
-
Typ  
Max Unit  
VCC for data retention  
Data retention current  
Data retention set-up time  
Recovery time  
CS1#  
VCC-0.2V (Note 1), BYTE# = VSS or VCC  
-
-
-
-
3.3  
TBD  
-
V
IDR  
VCC=3.0V, CS1#  
VCC-0.2V (Note 1)  
µA  
tSDR  
tRDR  
0
See data retention waveform  
ns  
tRC  
-
Notes:  
1. CS1 controlled:CS1#VCC-0.2V. CS2 controlled: CS2 0.2V.  
Timing Diagrams  
tRC  
Address  
tAA  
tOH  
Data Out  
Previous Data Valid  
Data Valid  
Figure 33. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB#  
and/or LB#=VIL)  
98  
S71GL032A Based MCPs  
S71GL032A_00_A0 March 31, 2005  
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