P R E L I M I N A R Y
ICC2 in the DC Characteristics table represents the active current specification for
the write mode. See the timing specification tables and timing diagrams in the
"Reset" section for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the
factory.
If the system asserts VHH on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin re-
turns the device to normal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin should be raised to VCC when not in
use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-
sistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. Refer to the "SecSiTM Sector Addresses"
section and "Autoselect Command Sequence" section for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in
PL129J) and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# (CE1#,CE#2 in PL129J) and RESET#
are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device requires standard access time
(tCE) for read access when the device is in either of these standby modes, before
it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
ICC3 in “DC Characteristics” represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at VIH before
the device reduces current to the stated sleep mode specification. ICC5 in “DC
Characteristics” represents the automatic sleep mode current specification.
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S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A62 April 7, 2005
SPANSION [ SPANSION ]
