D a t a S h e e t ( P r e l i m i n a r y )
11.7.4
S29GL-P Alternate CE# Controlled Erase and Program Operations
Table 11.7 S29GL-P Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
Description
JEDEC
tAVAV
Std.
tWC
tAS
tASO
tAH
tAHT
tDS
(Notes)
90
Min 90
Min
100
110
110
0
120 130 Unit
Write Cycle Time (Note 1)
100
120 130
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVWL
Address Setup Time
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
Min
15
45
0
tELAX
Min
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
Min
tDVEH
tEHDX
Min
30
0
tDH
Data Hold Time
Min
tCEPH
CE# High during toggle bit polling
Min
20
20
tOEPH OE# High during toggle bit polling
Min
Read Recovery Time Before Write
tGHEL
tGHEL
Min
0
ns
(OE# High to WE# Low)
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
µs
CE# Pulse Width
CE# Pulse Width High
35
30
480
15
tCPH
tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation (Notes 2, 4)
Per Word Typ
Per Word Typ
Effective Accelerated Write Buffer Program Operation
(Notes 2, 4)
13.5
µs
Program Operation (Note 2)
Accelerated Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Word
Word
Typ
Typ
Typ
60
54
µs
µs
0.5
sec
Notes
1. Not 100% tested.
2. See AC Characteristics on page 56 for more information.
3. For 1–32 words/1–64 bytes programmed.
4. Effective write buffer specification is based upon a 32-word/64-byte write buffer operation.
5. Unless otherwise indicated, AC specifications are tested with V = 1.8 V and V = 3.0 V.
IO
CC
64
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
SPANSION [ SPANSION ]
