S29GL128P90FAIR12 参数 Datasheet PDF下载

Da ta

Shee t

(Prelimi nar y)

Figure 11.13

Toggle Bit Timings (During Embedded Algorithms)

t

AHT

Addresses

t

AHT

t

ASO

CE#

t

OEH

WE#

t

OEPH

OE#

t

DH

DQ2 and DQ6

Valid Data

Valid

Status

t

AS

t

CEPH

t

OE

Valid

Status

Valid

Status

Valid Data

(first read)

RY/BY#

(second read)

(stops toggling)

Note

A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle

CE# does not need to go high between status bit reads

Figure 11.14

DQ2 vs. DQ6

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase

Enter Erase

Suspend Program

Erase

Suspend

Program

Erase

Resume

Erase Suspend

Read

Erase

Erase

Complete

Erase Suspend

Read

DQ6

DQ2

Note

DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE# or CE# to toggle DQ2 and DQ6.

November 8, 2007 S29GL-P_00_A7

S29GL-P MirrorBit

®

Flash Family

63