欢迎访问ic37.com |
会员登录 免费注册
发布采购

S29GL128P90FAIR12 参数 Datasheet PDF下载

S29GL128P90FAIR12图片预览
型号: S29GL128P90FAIR12
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有90纳米的MirrorBit工艺技术 [3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology]
分类和应用: 闪存
文件页数/大小: 77 页 / 2742 K
品牌: SPANSION [ SPANSION ]
 浏览型号S29GL128P90FAIR12的Datasheet PDF文件第62页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第63页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第64页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第65页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第67页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第68页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第69页浏览型号S29GL128P90FAIR12的Datasheet PDF文件第70页  
D a t a S h e e t ( P r e l i m i n a r y )  
11.7.5  
Erase And Programming Performance  
Table 11.8 Erase And Programming Performance  
Typ  
(Note 1)  
Max  
(Note 2)  
Parameter  
Unit  
Comments  
Sector Erase Time  
Chip Erase Time  
0.5  
64  
3.5  
256  
sec  
S29GL128P  
S29GL256P  
S29GL512P  
S29GL01GP  
Excludes 00h programming  
prior to erasure (Note 5)  
128  
256  
512  
480  
512  
sec  
1024  
2048  
Total Write Buffer Time (Note 3)  
µs  
µs  
Total Accelerated Write Buffer Programming Time  
(Note 3)  
432  
Excludes system level  
overhead (Note 6)  
S29GL128P  
123  
246  
492  
984  
S29GL256P  
Chip Program Time (Note 4)  
S29GL512P  
sec  
S29GL01GP  
Notes  
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V , 10,000 cycles, checkerboard pattern.  
CC  
2. Under worst case conditions of -40°C, V = 3.0 V, 100,000 cycles.  
CC  
3. Effective write buffer specification is based upon a 32-word write buffer operation.  
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum  
program times listed.  
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.  
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 12.112.4.  
11.7.6  
TSOP Pin and BGA Package Capacitance  
Table 11.9 Package Capacitance  
Parameter Symbol  
Parameter Description  
Input Capacitance  
Test Setup  
VIN = 0  
Typ  
6
Max  
10  
Unit  
pF  
CIN  
COUT  
CIN2  
Output Capacitance  
Control Pin Capacitance  
Separated Control Pin  
Separated Control Pin  
VOUT = 0  
VIN = 0  
10  
8
12  
pF  
10  
pF  
RESET#, WP#/ACC  
CE#  
V
IN = 0  
42  
22  
45  
pF  
VIN = 0  
25  
pF  
Notes  
1. Sampled, not 100% tested.  
2. Test conditions T = 25°C, f = 1.0 MHz.  
A
66  
S29GL-P MirrorBit® Flash Family  
S29GL-P_00_A7 November 8, 2007