D a t a S h e e t ( P r e l i m i n a r y )
Table 11.5 Power-up Sequence Timings
Parameter
Description
Speed
Unit
Reset Low Time from rising edge of VCC (or last Reset pulse) to
rising edge of RESET#
tVCS
Min
35
µs
Reset Low Time from rising edge of VIO (or last Reset pulse) to
rising edge of RESET#
tVIOS
tRH
Min
Min
35
µs
ns
Reset High Time before Read
200
Notes
1.
V
< V + 200 mV.
CC
IO
2.
V
and V ramp must be synchronized during power up.
IO
CC
3. If RESET# is not stable for t
or t
:
VCS
VIOS
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4.
V
maximum power-up current (RST=V ) is 20 mA.
C
C
I
L
Figure 11.8 Power-up Sequence Timings
V
CC
V
V
min
min
CC
V
IO
IO
t
RH
CE#
t
VIOS
t
VCS
RESET#
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
59
SPANSION [ SPANSION ]
