D a t a S h e e t
Test Conditions
3.3 V
2.7 k
Ω
Device
Under
Test
C
L
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Figure 9. Te st S e tup
Table 17. Test Specifications
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–VIO
Input timing measurement reference levels (See
Note)
0.5VIO
V
V
Output timing measurement reference levels
0.5 VIO
Note: If V < V , the reference level is 0.5 V .
IO
IO
CC
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
75