D a t a S h e e t
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed (Note 2)
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (Note 1)
tReady
Max
Max
20
ns
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (Note 1)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Reset High Time Before Read (Note 1)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Notes:
1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the RESET# pin needs to
be held low only for 100µs for power-up.
2. Next generation devices may have different reset speeds. To increase system design considerations, please refer to the “Advance
Information on S29GL-P Hardware Reset (RESET#) and Power-up Sequence” section for advance reset speeds on S29GL-P devices.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
tRH
Figure 13. Reset Timings
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
79
SPANSION [ SPANSION ]
