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S29GL128N11TAIV10 参数 Datasheet PDF下载

S29GL128N11TAIV10图片预览
型号: S29GL128N11TAIV10
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有110纳米MirrorBit⑩工艺技术 [3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology]
分类和应用: 闪存
文件页数/大小: 100 页 / 2678 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t  
DQ2: Toggle Bit II  
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is ac-  
tively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector  
is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the  
command sequence.  
DQ2 toggles when the system reads at addresses within those sectors that have been se-  
lected for erasure. (The system may use either OE# or CE# to control the  
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is  
erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is  
in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both  
status bits are required for sector and mode information. Refer to Table 16 on page 72 to  
compare outputs for DQ2 and DQ6.  
Figure 6, on page 70 shows the toggle bit algorithm in flowchart form, and the section DQ2:  
Toggle Bit II explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure  
18, on page 84 shows the toggle bit timing diagram. Figure 19, on page 84 shows the differ-  
ences between DQ2 and DQ6 in graphical form.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 6, on page 70 and Figure 19, on page 84 for the following discussion. When-  
ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice  
in a row to determine whether a toggle bit is toggling. Typically, the system would note and  
store the value of the toggle bit after the first read. After the second read, the system would  
compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the  
device has completed the program or erase operation. The system can read array data on  
DQ7–DQ0 on the following read cycle.  
However, if after the initial two read cycles, the system determines that the toggle bit is still  
toggling, the system also should note whether the value of DQ5 is high (see the section on  
DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the program or erase operation. If it is still  
toggling, the device did not completed the operation successfully, and the system must write  
the reset command to return to reading array data.  
The remaining scenario is that the system initially determines that the toggle bit is toggling  
and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5  
through successive read cycles, determining the status as described in the previous para-  
graph. Alternatively, it may choose to perform other system tasks. In this case, the system  
must start at the beginning of the algorithm when it returns to determine the status of the  
operation (top of Figure 6, on page 70).  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified  
internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the pro-  
gram or erase cycle was not successfully completed.  
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was  
previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under  
this condition, the device halts the operation, and when the timing limit is exceeded, DQ5 pro-  
duces a 1.  
In all these cases, the system must write the reset command to return the device to the read-  
ing the array (or to erase-suspend-read if the device was previously in the  
erase-suspend-program mode).  
S29GL-N_00_B3 October 13, 2006  
S29GL-N MirrorBit™ Flash Family  
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