D a t a S h e e t
as in the standard program operation. See Write Operation Status‚ on page 67 for more
information.
The system must write the Program Resume command (address bits are don’t care) to exit
the Program Suspend mode and continue the programming operation. Further writes of the
Resume command are ignored. Another Program Suspend command can be written after the
device has resume programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 μs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 3. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the chip erase command, which in turn invokes the Embedded Erase algo-
rithm. The device does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any controls or timings
during these operations. Table 12 on page 63 and Table 14 on page 65 show the address and
data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and
addresses are no longer latched. The system can determine the status of the erase operation
by using DQ7, DQ6, or DQ2. Refer to Write Operation Status‚ on page 67 for information on
these status bits.
Any commands written during the chip erase operation are ignored, including erase suspend
commands. However, note that a hardware reset immediately terminates the erase opera-
56
S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
