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AM29LV640MH112RPCI 参数 Datasheet PDF下载

AM29LV640MH112RPCI图片预览
型号: AM29LV640MH112RPCI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位/ 8的M× 8位)的MirrorBit 3.0伏特,只有统一部门快闪记忆体与VersatileI / O控制 [64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control]
分类和应用: 闪存内存集成电路
文件页数/大小: 62 页 / 1108 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
Table 7. Primary Vendor-Specific Extended Query  
Addresses Addresses  
(x16)  
(x8)  
Data  
Description  
40h  
41h  
42h  
80h  
82h  
84h  
0050h  
0052h  
0049h  
Query-unique ASCII string “PRI”  
43h  
44h  
86h  
88h  
0031h  
0033h  
Major version number, ASCII  
Minor version number, ASCII  
Address Sensitive Unlock (Bits 1-0)  
0 = Required, 1 = Not Required  
45h  
8Ah  
0008h  
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit  
Erase Suspend  
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write  
46h  
47h  
48h  
49h  
4Ah  
4Bh  
4Ch  
8Ch  
8Eh  
90h  
92h  
94h  
96h  
98h  
0002h  
0001h  
0001h  
0004h  
0000h  
0000h  
0001h  
Sector Protect  
0 = Not Supported, X = Number of sectors in per group  
Sector Temporary Unprotect  
00 = Not Supported, 01 = Supported  
Sector Protect/Unprotect scheme  
04 = 29LV800 mode  
Simultaneous Operation  
00 = Not Supported, X = Number of Sectors in Bank  
Burst Mode Type  
00 = Not Supported, 01 = Supported  
Page Mode Type  
00 = Not Supported, 01 = 4 Word/8 Byte Page, 02 = 8 Word/16 Byte Page  
ACC (Acceleration) Supply Minimum  
4Dh  
4Eh  
9Ah  
9Ch  
00B5h  
00C5h  
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV  
ACC (Acceleration) Supply Maximum  
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV  
Top/Bottom Boot Sector Flag  
0004h/  
0005h  
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top  
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top  
WP# protect  
4Fh  
50h  
9Eh  
A0h  
Program Suspend  
0001h  
00h = Not Supported, 01h = Supported  
COMMAND DEFINITIONS  
Writing specific address and data commands or se-  
quences into the command register initiates device op-  
erations. Tables 10 and 11 define the valid register  
command sequences. Writing incorrect address and  
data values or writing them in the improper se-  
quence may place the device in an unknown state. A  
reset command is then required to return the device to  
reading array data.  
after completing an Embedded Program or Embedded  
Erase algorithm.  
After the device accepts an Erase Suspend command,  
the device enters the erase-suspend-read mode, after  
which the system can read data from any  
non-erase-suspended sector. After completing a pro-  
gramming operation in the Erase Suspend mode, the  
system may once again read array data with the same  
exception. See the Erase Suspend/Erase Resume  
Commands section for more information.  
All addresses are latched on the falling edge of WE#  
or CE#, whichever happens later. All data is latched on  
the rising edge of WE# or CE#, whichever happens  
first. Refer to the AC Characteristics section for timing  
diagrams.  
The system must issue the reset command to return  
the device to the read (or erase-suspend-read) mode if  
DQ5 goes high during an active program or erase op-  
eration, or if the device is in the autoselect mode. See  
the next section, Reset Command, for more informa-  
tion.  
Reading Array Data  
The device is automatically set to reading array data  
after device power-up. No commands are required to  
retrieve data. The device is ready to read array data  
See also Requirements for Reading Array Data in the  
Device Bus Operations section for more information.  
24  
Am29LV640MH/L  
December 14, 2005