欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM29LV640MH112RPCI 参数 Datasheet PDF下载

AM29LV640MH112RPCI图片预览
型号: AM29LV640MH112RPCI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位/ 8的M× 8位)的MirrorBit 3.0伏特,只有统一部门快闪记忆体与VersatileI / O控制 [64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control]
分类和应用: 闪存内存集成电路
文件页数/大小: 62 页 / 1108 K
品牌: SPANSION [ SPANSION ]
 浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第19页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第20页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第21页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第22页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第24页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第25页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第26页浏览型号AM29LV640MH112RPCI的Datasheet PDF文件第27页  
D A T A S H E E T  
START  
If data = 00h,  
RESET# =  
VIH or VID  
SecSi Sector is  
unprotected.  
If data = 01h,  
SecSi Sector is  
protected.  
Wait 1 ms  
Write 60h to  
any address  
Remove VIH or VID  
from RESET#  
Write 40h to SecSi  
Sector address  
with A6 = 0,  
Write reset  
command  
A1 = 1, A0 = 0  
SecSi Sector  
Protect Verify  
complete  
Read from SecSi  
Sector address  
with A6 = 0,  
A1 = 1, A0 = 0  
Figure 3. SecSi Sector Protect Verify  
pins to prevent unintentional writes when VCC is  
greater than VLKO  
Hardware Data Protection  
.
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection  
against inadvertent writes (refer to Tables 10 and 11  
for command definitions). In addition, the following  
hardware data protection measures prevent accidental  
erasure or programming, which might otherwise be  
caused by spurious system level signals during VCC  
power-up and power-down transitions, or from system  
noise.  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE#  
or WE# do not initiate a write cycle.  
Logical Inhibit  
Write cycles are inhibited by holding any one of OE# =  
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,  
CE# and WE# must be a logical zero while OE# is a  
logical one.  
Low VCC Write Inhibit  
When VCC is less than VLKO, the device does not ac-  
cept any write cycles. This protects data during VCC  
power-up and power-down. The command register  
and all internal program/erase circuits are disabled,  
and the device resets to the read mode. Subsequent  
writes are ignored until VCC is greater than VLKO. The  
system must provide the proper signals to the control  
Power-Up Write Inhibit  
If WE# = CE# = VIL and OE# = VIH during power up,  
the device does not accept commands on the rising  
edge of WE#. The internal state machine is automati-  
cally reset to the read mode on power-up.  
COMMON FLASH MEMORY INTERFACE (CFI)  
The Common Flash Interface (CFI) specification out-  
lines device and host system software interrogation  
handshake, which allows specific vendor-specified  
software algorithms to be used for entire families of  
devices. Software support can then be device-inde-  
pendent, JEDEC ID-independent, and forward- and  
backward-compatible for the specified flash device  
families. Flash vendors can standardize their existing  
interfaces for long-term compatibility.  
55h, any time the device is ready to read array data.  
The system can read CFI information at the addresses  
given in Tables 69. To terminate reading CFI data,  
the system must write the reset command.  
The system can also write the CFI query command  
when the device is in the autoselect mode. The device  
enters the CFI query mode, and the system can read  
CFI data at the addresses given in Tables 69. The  
system must write the reset command to return the  
device to reading array data.  
This device enters the CFI Query mode when the sys-  
tem writes the CFI Query command, 98h, to address  
December 14, 2005  
Am29LV640MH/L  
21