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AM29DL640H70WHI 参数 Datasheet PDF下载

AM29DL640H70WHI图片预览
型号: AM29DL640H70WHI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 54 页 / 1243 K
品牌: SPANSION [ SPANSION ]
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cured Silicon Sector region by issuing the three-cycle  
Enter Secured Silicon Sector command sequence.  
The device continues to access the Secured Silicon  
Sector region until the system issues the four-cycle  
Exit Secured Silicon Sector command sequence. The  
Exit Secured Silicon Sector command sequence re-  
turns the device to normal operation. The Secured Sil-  
icon Sector is not accessible when the device is  
executing an Embedded Program or embedded Erase  
algorithm. Table 12 shows the address and data re-  
quirements for both command sequences. See also  
“Secured Silicon Sector Flash Memory Region” for fur-  
ther information. Note that the ACC function and un-  
lock bypass modes are not available when the  
Secured Silicon Sector is enabled.  
from “0” back to a “1.Attempting to do so may  
cause that bank to set DQ5 = 1, or cause the DQ7 and  
DQ6 status bits to indicate the operation was success-  
ful. However, a succeeding read will show that the  
data is still “0.Only erase operations can convert a “0”  
to a “1.”  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to pro-  
gram bytes or words to a bank faster than using the  
standard program command sequence. The unlock  
bypass command sequence is initiated by first writing  
two unlock cycles. This is followed by a third write  
cycle containing the unlock bypass command, 20h.  
That bank then enters the unlock bypass mode. A  
two-cycle unlock bypass program command sequence  
is all that is required to program in this mode. The first  
cycle in this sequence contains the unlock bypass pro-  
gram command, A0h; the second cycle contains the  
program address and data. Additional data is pro-  
grammed in the same manner. This mode dispenses  
with the initial two unlock cycles required in the stan-  
dard program command sequence, resulting in faster  
total programming time. Table 12 shows the require-  
ments for the command sequence.  
Byte/Word Program Command Sequence  
The system may program the device by word or byte,  
depending on the state of the BYTE# pin. Program-  
ming is a four-bus-cycle operation. The program com-  
mand sequence is initiated by writing two unlock write  
cycles, followed by the program set-up command. The  
program address and data are written next, which in  
turn initiate the Embedded Program algorithm. The  
system is not required to provide further controls or  
timings. The device automatically provides internally  
generated program pulses and verifies the pro-  
grammed cell margin. Table 12 shows the address and  
data requirements for the byte program command se-  
quence.  
During the unlock bypass mode, only the Unlock By-  
pass Program and Unlock Bypass Reset commands  
are valid. To exit the unlock bypass mode, the system  
must issue the two-cycle unlock bypass reset com-  
mand sequence. (See Table 12).  
When the Embedded Program algorithm is complete,  
that bank then returns to the read mode and ad-  
dresses are no longer latched. The system can deter-  
mine the status of the program operation by using  
DQ7, DQ6, or RY/BY#. Refer to the Write Operation  
Status section for information on these status bits.  
The device offers accelerated program operations  
through the WP#/ACC pin. When the system asserts  
VHH on the WP#/ACC pin, the device automatically en-  
ters the Unlock Bypass mode. The system may then  
write the two-cycle Unlock Bypass program command  
sequence. The device uses the higher voltage on the  
WP#/ACC pin to accelerate the operation. Note that  
the WP#/ACC pin must not be at VHH for any operation  
other than accelerated programming, or device dam-  
age may result. In addition, the WP#/ACC pin must not  
be left floating or unconnected; inconsistent behavior  
of the device may result.  
Any commands written to the device during the Em-  
bedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the program  
operation. The program command sequence should  
be reinitiated once that bank has returned to the read  
mode, to ensure data integrity. Note that the Secured  
Silicon Sector, autoselect, and CFI functions are un-  
available when a program operation is in progress.  
Figure 4 illustrates the algorithm for the program oper-  
ation. Refer to the Erase and Program Operations  
table in the AC Characteristics section for parameters,  
and Figure 18 for timing diagrams.  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed  
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Am29DL640H  
June 7, 2005  
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