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AM29DL640H70WHI 参数 Datasheet PDF下载

AM29DL640H70WHI图片预览
型号: AM29DL640H70WHI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 54 页 / 1243 K
品牌: SPANSION [ SPANSION ]
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Table 12. Am29DL640H Command Definitions  
Bus Cycles (Notes 2–5)  
Command  
Sequence  
(Note 1)  
First  
Second  
Third  
Addr  
Fourth  
Fifth  
Addr  
Sixth  
Addr  
Addr Data Addr Data  
Data  
Addr  
Data  
Data  
Data  
Read (Note 6)  
Reset (Note 7)  
1
1
RA  
XXX  
555  
AAA  
555  
AAA  
555  
RD  
F0  
Word  
Byte  
Word  
Byte  
2AA  
555  
2AA  
555  
2AA  
(BA)555  
(BA)AAA  
(BA)555  
(BA)AAA  
(BA)555  
Manufacturer ID  
Device ID (Note 9)  
4
6
AA  
AA  
55  
55  
90 (BA)X00  
01  
(BA)X01  
90  
(BA)X0E  
(BA)X1C  
(BA)X0F  
(BA)X1E  
7E  
02  
01  
(BA)X02  
Secured Silicon Sector Word  
(BA)X03  
Factory Protect (Note  
10)  
4
4
AA  
AA  
55  
55  
90  
81/01  
00/01  
Byte  
AAA  
555  
555  
2AA  
555  
(BA)AAA  
(BA)555  
(BA)AAA  
(BA)X06  
Sector/Sector Block  
Protect Verify  
(Note 11)  
Word  
Byte  
(SA)X02  
90  
AAA  
(SA)X04  
Word  
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
555  
AAA  
555  
AAA  
555  
AAA  
555  
AAA  
XXX  
XXX  
555  
AAA  
555  
AAA  
BA  
2AA  
555  
2AA  
555  
2AA  
555  
2AA  
555  
PA  
555  
AAA  
555  
Enter Secured Silicon  
Sector Region  
3
4
4
3
AA  
AA  
AA  
AA  
55  
55  
55  
55  
88  
Exit Secured Silicon Sector  
Region  
90  
A0  
20  
XXX  
PA  
00  
AAA  
555  
Program  
PD  
AAA  
555  
Unlock Bypass  
AAA  
Unlock Bypass Program (Note 12)  
Unlock Bypass Reset (Note 13)  
2
2
A0  
90  
PD  
00  
XXX  
2AA  
555  
2AA  
555  
Word  
555  
AAA  
555  
555  
AAA  
555  
2AA  
555  
2AA  
555  
555  
Chip Erase  
Byte  
6
6
AA  
AA  
55  
55  
80  
80  
AA  
AA  
55  
55  
10  
30  
AAA  
Word  
Sector Erase  
Byte  
SA  
AAA  
AAA  
Erase Suspend (Note 14)  
Erase Resume (Note 15)  
1
1
B0  
30  
BA  
Word  
CFI Query (Note 16)  
Byte  
55  
1
98  
AA  
Legend:  
X = Don’t care  
PD = Data to be programmed at location PA. Data latches on the rising  
edge of WE# or CE# pulse, whichever happens first.  
RA = Address of the memory location to be read.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed. Addresses  
latch on the falling edge of the WE# or CE# pulse, whichever happens  
later.  
SA = Address of the sector to be verified (in autoselect mode) or  
erased. Address bits A21–A12 uniquely select any sector. Refer to  
Table 2 for information on sector addresses.  
BA = Address of the bank that is being switched to autoselect mode, is  
in bypass mode, or is being erased. A21–A19 uniquely select a bank.  
Notes:  
1. See Table 1 for description of bus operations.  
2. All values are in hexadecimal.  
9. The device ID must be read across the fourth, fifth, and sixth  
cycles.  
10. The data is 81h for factory locked, 40h for customer locked, and  
01h for not factory/customer locked.  
11. The data is 00h for an unprotected sector/sector block and 01h for  
a protected sector/sector block.  
12. The Unlock Bypass command is required prior to the Unlock  
Bypass Program command.  
13. The Unlock Bypass Reset command is required to return to the  
read mode when the bank is in the unlock bypass mode.  
14. The system may read and program in non-erasing sectors, or  
enter the autoselect mode, when in the Erase Suspend mode.  
The Erase Suspend command is valid only during a sector erase  
operation, and requires the bank address.  
15. The Erase Resume command is valid only during the Erase  
Suspend mode, and requires the bank address.  
16. Command is valid when device is ready to read array data or when  
device is in autoselect mode.  
3. Except for the read cycle and the fourth, fifth, and sixth cycle of  
the autoselect command sequence, all bus cycles are write  
cycles.  
4. Data bits DQ15–DQ8 are don’t care in command sequences,  
except for RD and PD.  
5. Unless otherwise noted, address bits A21–A11 are don’t cares for  
unlock and command cycles, unless SA or PA is required.  
6. No unlock or command cycles required when bank is reading  
array data.  
7. The Reset command is required to return to the read mode (or to  
the erase-suspend-read mode if previously in Erase Suspend)  
when a bank is in the autoselect mode, or if DQ5 goes high (while  
the bank is providing status information).  
8. The fourth cycle of the autoselect command sequence is a read  
cycle. The system must provide the bank address to obtain the  
manufacturer ID, device ID, or Secured Silicon Sector factory  
protect information. Data bits DQ15–DQ8 are don’t care. While  
reading the autoselect addresses, the bank address must be the  
same until a reset command is given. See the Autoselect  
Command Sequence section for more information.  
June 7, 2005  
Am29DL640H  
27  
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